Since the 1990's, integrated circuit (IC) design has evolved from a chip-set philosophy to an embedded core based SoC concept. An SoC IC includes various reusable functional blocks, such as microprocessors, interfaces, memory arrays, and DSPs (digital signal processors). Such pre-designed functional blocks are commonly called “IP cores,” “cores,” or “blocks”, and are collectively referred to herein as “functional blocks,” or simply, “blocks.” The resulting SoCs have become quite complex. Moreover, the techniques used in the design of these SoCs have not scaled with the complexities of chip designs. That is, SoCs are currently designed by lumping functional blocks from different vendors into a single design and then functionally verifying the interfaces between these blocks.
Debugging SoCs can be a difficult task after a design has been fabricated. This difficulty is due to the numerous possible interactions between different functional blocks. Quite often, the type of problems that go undetected during the design process are those that involve interactions between different functional blocks. Designers typically write exhaustive functional tests to verify the functionality of their designs in a standalone environment. When the functional block is integrated, additional functional tests are then written to check the interface to the block. However, these tests are non-exhaustive, system-level tests. The lack of system-level tests is due to the limited understanding that a block designer has of the system in which his block will be used.
When functional problems do occur with fabricated SoCs, designers attempt to determine the cause by observing the state of internal registers, internal memories, or the output signals presented at the pins to the device (e.g., by various means such as test probing of device pins as well as more sophisticated methods employing computer driven debugging interfaces). Frequently, this is accompanied by well known prior art debugging techniques such as breakpointing. Breakpointing is a concept used in microprocessor design to allow software designers to efficiently debug their code. The designer sets a breakpoint on an instruction to be executed by the microprocessor. Prior to the microprocessor executing that instruction, instruction flow is halted, and the microprocessor enters debug mode.
Single-cycle stepping or n-cycle stepping is another debugging concept that is used in conjunction with breakpointing to allow software designers to efficiently debug their code. The designer sets a breakpoint on an instruction to be executed by the microprocessor. As described above, prior to the microprocessor executing that instruction, instruction flow is halted, and the microprocessor enters debug mode. To allow single-stepping, a breakpoint is set on the following instruction, and the microprocessor is released from debug mode to execute the current instruction before entering debug mode again. Similarly, for n-cycle stepping, a breakpoint is set on the instruction that is n-instructions ahead.
These prior art debugging techniques are not readily applicable to complex SoCs. This dilemma can be attributed to there being multiple blocks running on different clock domains, and each block potentially having its own method for halting the execution. Current SoCs have separated the breakpointing mechanisms of different functional blocks to simplify the design process. This design approach hampers the designer when debugging failures on SoCs. In particular, the designer needs to halt each functional block separately, and as a result, there is no control over the entire SoC device up to the point of failure.
Further, for such complex SoCs, there is no previously described technique to single or n-cycle step the entire SoC. Again, this dilemma can be attributed to there being multiple blocks running on different clock domains, as well as each block potentially having its own method for single or n-cycle stepping the execution.
The present invention overcomes these problems in the prior art by providing a means to halt the execution of a SoC and to provide a means to single or n-cycle step the execution of the SoC by effectively controlling the clocks within the SoC.